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INTEGRATED CIRCUITS
DATA SHEET
TDA9802 Multistandard VIF-PLL demodulator and FM-PLL detector
Preliminary specification File under Integrated Circuits, IC02 November 1992
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
FEATURES * Suitable for negative and positive vision modulation * Gain controlled 3-stage IF amplifier; suitable for VIF frequencies up to 60 MHz * True synchronous demodulation with active carrier regeneration (ultra-linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response) * Peak sync AGC for negative modulation, e.g. B/G standard * Peak white AGC for positive modulation, e.g. L standard * Video amplifier to match sound trap and sound filter
TDA9802
* AGC output voltage for tuner; adjustable take-over point (TOP) * AFC detector without extra reference circuit * Alignment-free FM-PLL detector with high linearity * Stabilizer circuit for ripple rejection and to achieve constant output signals * 5 to 8 V positive supply voltage range, low power consumption (300 mW at +5 V supply voltage) GENERAL DESCRIPTION The TDA9802 is a monolithic integrated circuit for vision and sound IF signal processing in multistandard TV and VTR sets.
QUICK REFERENCE DATA SYMBOL VP IP Vi IF Gv Vo CVBS B S/N (W) 1.1 3.3 H Vo AF Tamb suppression of harmonics in video signal maximum AF output signal for THD < 1.5% (RMS value, pin 9) operating ambient temperature range supply current PARAMETER positive supply voltage (pin 20) 51 MIN. 4.5 5 60 50 150 70 2.0 8 59 62 62 40 - - TYP. MAX. 8.8 69 90 - 73 2.3 - - - - - - +70 V mA V mV dB V MHz dB dB dB dB V C UNIT
vision IF input signal sensitivity (RMS value, pins 1 and 2) - maximum vision IF input signal (RMS value, pins 1 and 2) 70 IF gain control range CVBS output signal on pin 7 (peak-to-peak value) -3 dB video bandwidth on pin 7 signal-to-noise ratio weighted; for video intermodulation attenuation 64 1.7 6 56 56 56 35 0.8 0
ORDERING INFORMATION EXTENDED TYPE NUMBER TDA9802 TDA9802T Note 1. SOT146-1; 1996 November 19. 2. SOT163-1; 1996 November 19. PACKAGE PINS 20 20 PIN POSITION DIL mini-pack MATERIAL plastic plastic CODE SOT146(1) SOT163A(2)
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
PINNING SYMBOL Vi IF TADJ ADJ CBL TPLL Vo CVBS STD Vo AF CAF Vi IC TAGC Vo VID Vi VID AFC VCO1 VCO2 GND CAGC VP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ground (0 V) AGC capacitor positive supply voltage tuner AGC take-over adjust (TOP) phase detector adjust black level capacitor, mute switch input PLL time constant of phase detector CVBS (positive) output signal standard switch (negative = HIGH, positive = LOW) audio frequency output signal decoupling capacitor of audio frequency amplifier sound intercarrier input signal tuner AGC output video and sound intercarrier output signal video input signal to buffer amplifier automatic frequency control output VCO reference circuit for 2 fPC DESCRIPTION vision IF differential input signal
TDA9802
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
FUNCTIONAL DESCRIPTION Vision IF input The vision IF amplifier consists of three AC-coupled differential amplifier stages; each stage comprises a controlled feedback network by means of emitter degeneration. IF and tuner AGC The automatic control voltage to maintain the video output signal at a constant level is generated according to the transmission standard. For negative modulation the peak-sync level is detected, for positive modulation the peak white level is detected. The AGC detector charges and discharges the capacitor on pin 19 to set the IF gain and the tuner gain. The standard is switched by the voltage on pin 8. To reduce the response time for positive modulation (which needs a very long time constant) a black level detector (CBL) increases the AGC capacitor discharge current for low-level video signals. The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current on pin 12 (open-collector output). The tuner AGC voltage take over point is adjusted on pin 3. This allows the tuner and the IF SAW filter to be matched to achieve the optimum IF input level. Frequency detector, phase detector and video demodulator The IF amplifier output signal is fed to a frequency detector and to a phase detector. The frequency detector is operational before lock-in. A DC current is generated which is proportional to the frequency difference between the input frequency and the VCO frequency. After lock-in, the frequency detector and the phase detector generate a DC current proportional to the phase difference between VCO and input signals. The control signal for the VCO is provided by the phase detector. The video demodulator is a linear multiplier, designed for low distortion and wide bandwidth. The vision IF input signal is multiplied by the in-phase component of the VCO output. The demodulated output signal is fed via an integrated low-pass filter (fg = 12 MHz) to the video amplifier for suppression of the carrier harmonics. The polarity of the video signal is switched in the demodulator stage according to the TV standard. VCO and travelling wave divider
TDA9802
The VCO operates with a symmetrically-connected reference LC-circuit, operating at double vision carrier frequency. Frequency control is performed by an internal varicap diode. The voltage to set the VCO frequency to the actual frequency of double vision carrier frequency, is also amplified and converted for the AFC output current. The VCO signal is divided-by-two in a travelling wave divider, which generates two differential output signals with 90 degree phase difference independent of frequency. Video amplifier, buffer and noise clipping The video amplifier is a wide bandwidth operational amplifier with internal feedback. Dependent on transmission standard, a level shifter provides the same sync level for positive as for negative modulation. A nominal positive modulated video signal of 1 V (p-p) is present on the composite video output (pin 13). The input impedance of the 7 dB wideband buffer amplifier (with internal feedback) is suitable for ceramic sound trap filters. The CVBS output (pin 7) provides a positive video signal of 2 V (p-p). Noise clipping is provided internally. Sound demodulation The FM sound intercarrier signal is fed to pin 11 and through a limiter amplifier before it is demodulated. This achieves high sensitivity and high AM suppression. The limiter amplifier consists of seven internal AC-coupled stages, minimizing the DC offset. The FM-PLL demodulator consists of an RC-oscillator, loop filter and phase detector. The oscillator frequency is locked on the FM intercarrier signal from the limiter amplifier. As a result of this locking, the RC-oscillator is frequency-modulated. The modulating signal voltage (AF signal) is used to control the oscillator frequency. By this, the FM-PLL operates as an FM demodulator. The audio frequency amplifier with internal feedback is designed for high gain and high common mode rejection. The low-level AF signal output from the FM-PLL demodulator is amplified and buffered in a low-ohmic audio signal output stage (pin 9). An external decoupling capacitor on pin 10 removes the DC voltage from the audio amplifier input.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134) SYMBOL VP SOT146 at + 120 C SO163A at + 100 C VI ts max V12 Tstg VESD voltage on pins 1, 2, 7, 8, 11, 13, 14, 15 and 19 short-circuit time tuner AGC output voltage storage temperature range electrostatic handling for all pins (note 2) PARAMETER supply voltage (pin 20) for a maximum chip temperature (note 1) 0 0 0 - - -25 - MIN.
TDA9802
MAX. 8.8 5.5 VP 10 13.2 +150 300 V V V s V
UNIT
C V
Notes to the Limiting Values 1. Supply current IP = 69 mA at Tamb = +70 C. 2. Equivalent to discharging a 200 pF capacitor through a 0 series resistor (negative and positive voltage). THERMAL RESISTANCE SYMBOL Rth j-a SOT146 SOT163A PARAMETER from junction to ambient in free air 73 K/W 85 K/W THERMAL RESISTANCE
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
CHARACTERISTICS VP = 5 V; Tamb = +25 C; fPC = 38.9 MHz; fSC = 33.4 MHz with VPC/VSC = 13 dB (B/G); ViIF = 10 mV RMS value (sync level at B/G; peak-white level at L); video modulation DSB; residual carrier: B/G = 10%, L = 3%; video signal in accordance with CCIR line 17; measurements taken in Fig.3 unless otherwise specified SYMBOL VP IP VIH VIL IIL Vi Vi GIF B Ri Ci V1, 2 fVCO fVCO Vo ref fPC tacqu Vi IF supply current PARAMETER supply voltage range (pin 20) CONDITIONS see note 1 MIN. 4.5 51 TYP. 5 60 - - MAX. 8.8 69 V mA UNIT
Standard switch input (pin 8) input voltage for negative modulation input voltage for positive modulation LOW level input current V8 = 0 V B/G standard -1 dB video at output +1 dB video at output - 70 - 64 70 1.7 1.2 3.0 see note 3 f = 2fPC see note 4; T = 0 to+70 C 125 - tbn 1.5 1.5 see note 5; BL = 60 kHz - 130 - 120 2 2 - - 1300 tbn - - 30 MHz 10-6 mV MHz MHz ms 50 150 0.7 70 100 2.2 1.7 3.4 90 - 1 73 - 2.7 2.5 3.8 V mV dB dB MHz k pF V see note 2 1.5 0 - VP 0.8 V V A
-300 -360
Vision IF input (pins 1 and 2) input signal sensitivity (RMS value) maximum input signal (RMS value)
IF amplitude difference between picture and within AGC range sound carrier IF gain control range -3 dB IF bandwidth input resistance input capacitance DC input voltage see Fig.4 upper cut-off frequency
True synchronous video demodulator maximum oscillator frequency for carrier regeneration oscillator drift (free running) as a function of temperature oscillator swing at pins 16 and 17 (RMS value) vision carrier capture range (negative) vision carrier capture range (positive) acquisition time IF input signal sensitivity (RMS value, pins 1 and 2) for PLL still locked for C/N = 10 dB Iloop FPLL loop offset current at pin 6
see note 6; maximum IF gain see note 7 see note 8
- - -
70 100 -
100 140 4.5
V V A
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SYMBOL PARAMETER CONDITIONS sound carrier off see Fig.7 B/G and L B/G L upper video clipping level lower video clipping level V0 FM R13 Iint13 I13 B H RR IF intercarrier level (RMS value) output resistance internal bias current for emitter follower maximum output sink current maximum output source current -3 dB video bandwidth suppression of video signal harmonics ripple rejection on pin 13 C13 < 50 pF; RL > 1 k see note 10; C13 < 50 pF; RL > 1 k see Fig.9 DC DC and AC sound carrier on; see note 9 0.9 1.4 2.5 1.37 VP - 1.1 - tbn - 1.8 1.4 2.0 7 35 32 1.0 1.5 2.6 1.47 VP - 1.0 0.3 140 - 2.5 tbn tbn 10 40 35 MIN. TYP.
TDA9802
MAX.
UNIT
Composite video amplifier (pin 13) V0 vid V13 output signal (peak-to-peak value) sync level zero carrier level
1.1 1.6 2.7 1.57 - 0.4 tbn 10 - - - - - -
V V V V V V mV mA mA mA MHz dB dB
CVBS buffer amplifier and noise clipper (pins 7 and 14) R14 C14 V14 Gv Vo CVBS input resistance input capacitance DC voltage at input voltage gain CVBS output signal on pin 7 (peak-to-peak value) CVBS output level pin 14 not connected see note 11 sound carrier off; see Fig.3 upper video clipping lower video clipping sync level R7 Iint7 I7 B output resistance internal bias current for emitter follower maximum output sink current maximum output source current -3 dB video bandwidth C7 < 20 pF; RL > 1 k DC DC and AC 2.6 1.4 1.5 6 1.7 tbn - 1.25 - 1.8 1.4 2.4 8 3.3 2 1.8 7 2.0 4.0 1.0 1.35 - 2.5 tbn tbn 11 4.0 3.0 2.1 7.5 2.3 - tbn 1.45 10 - - - - k pF V dB V V V V mA mA mA MHz
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9802
MAX.
UNIT
Measurements from IF input to CVBS output (pin 7) 330 between pins 13 and 14, sound carrier off Vo CVBS Vo CVBS output signal on pin 7 (peak-to-peak value) deviation of CVBS output signal at B/G black level tilt vertical tilt for worst case in L standard 50 dB gain control 30 dB gain control B/G standard; see note 12 vision carrier modulated by test line (VITS) only; see note 12 1.7 - - - - 2.0 - - - - 2.3 0.5 0.1 1 1.5 V dB dB % %
G B S/N(W) 1.1 3.3 C H RR
differential gain differential phase -3 dB video bandwidth signal-to-noise ratio; weighted intermodulation at `blue' intermodulation at `yellow' intermodulation at `blue' intermodulation at `yellow' residual vision carrier (RMS value) suppression of video signal harmonics ripple rejection on pin 7 CL < 20 pF; RL > 1 k see Fig.5 and note 13 see Fig.6 and note 14; f = 1.1 MHz see Fig.6 and note 14; f = 3.3 MHz fundamental wave harmonics see note 10 see Fig.9
- - 6 56 56 58 56 57 - - 35 25 - - - 0.85 2.0
2 1 8 59 62 64 62 63 1 1 40 28
5 3 - - - - - - 10 10 - -
% deg MHz dB dB dB dB dB mV mV dB dB
AGC detector (pin 19) tresp response to an increasing amplitude step of 50 dB in input signal response to a decreasing amplitude step of 50 dB in input signal I19 charging current additional charging current B/G and L B/G L B/G and L; see note 12 L in case of missing VITS pulses and no white video content B/G normal mode L fast mode L V19 AGC voltage see Fig.4 maximum gain minimum gain V13 threshold voltage level for additional charging current for fast L mode see Fig.7 L L 1.9 1.6 1.95 1.65 2.0 1.7 V V 0 - tbn tbn - V VP - 0.7 V 1 50 100 1.1 2.7 10 100 150 1.35 3.5 ms ms ms mA A
discharging current
17 0.24 31
22 0.33 44
27 0.42 57
A A A
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SYMBOL Tuner AGC (pin 12) Vi IF input signal for minimum starting point of tuner take over (RMS value) IF input signal for maximum starting point of tuner take over (RMS value) V12 V12 I12 allowable voltage saturation voltage variation of take over point by temperature sink current input at pins 1 and 2; RTOP = 22 k input at pins 1 and 2; RTOP = 0 from external source I12 = 1.7 mA T = 0 to +50 C see Fig.4 no tuner gain reduction maximum tuner gain reduction GIF IF slip by automatic gain control tuner gain current from 20 to 80% see Fig.8 and note 15 see note 16 T = 0 to +70 C; see note 4 see Fig.8 0.6 - VP - 0.5 - 160 160 B/G and L see note 17 0 1.5 V5 = 0 V V5 = 0 V switching to MUTE-ON FM 5.5 MHz CCIR468-4 see Fig.11 AM: f = 1 kHz; m = 0.3 - - 200 480 lower and upper cut-off frequency 3.5 2.3 200 1 - 600 - 2.6 - 70 - - - 80 100 - 0.72 - VP - 0.3 0.3 200 200 20 - 1.7 - 0.1 2.0 6 - 50 - - - - - - - 1 5 - PARAMETER CONDITIONS MIN. TYP.
TDA9802
MAX.
UNIT
mV mV V V dB A mA dB
13.2 0.2 3 0.3 2.6 8
AFC circuit (pin 15) S fIF V15 control steepness I15/f frequency variation by temperature output voltage upper limit output voltage lower limit I15 I15 output current source output current sink residual video modulation current (peak-to-peak value)
0.84 1300 - 0.5 240 240 30
A/kHz 10-6 V V A A A
Sound mute switch (pin 5) VIL VIH IIL mute V5 Vi FM input voltage for MUTE-ON input voltage for MUTE-OFF LOW level input current audio attenuation DC offset voltage at switching (plop)
0.8 VP - 500
V V A dB mV
-300 -360
FM sound limiter amplifier (pin 11) input signal (RMS value, pin 11) for S/N = 40 dB for AM suppression AM = 40 dB maximum input signal handling (RMS value) R11 B V11 input resistance -3 dB IF frequency response of sound IF DC voltage
300 - - 720 10 2.9
V mV mV MHz V
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SYMBOL PARAMETER CONDITIONS see note 18 4 3.5 - THD < 1.5%; see note 19 voltage dependent on VCO frequency; see note 20 fAF = 27 kHz; see Fig.11 THD < 1.5% T = 0 to+70 C - 1.2 - - - - - 7 8 4 MIN. TYP.
TDA9802
MAX.
UNIT
FM-PLL sound demodulator and AF output (pin 9) fi FM tacqu fAF V10 catching range of PLL holding range of PLL acquisition time frequency deviation DC voltage at decoupling capacitor
MHz MHz s kHz V
50 2.2
Vo AF
AF output signal (RMS value, pin 9) maximum output signal handling
280 0.8 - - 2.2 1.6 95 -
350 - 0.2 100 - 2.0 120 0.1 55 - 50 30
420 - 0.5 - - 2.4 - 0.5 - 75 - -
mV V dB k V kHz % dB mV dB dB
Vo R9 RL V9 B THD S/N (W) VSC AM RR
temperature drift of AF output signal output resistance load resistance (pin 9) DC voltage -3 dB audio frequency bandwidth total harmonic distortion signal-to-noise ratio, weighted residual sound carrier and harmonics (RMS value) AM suppression ripple rejection on pin 9
CCIR468-4; see Fig.11
50 -
see Fig.10; AM: f = 1 kHz; m = 0.3 see Fig.9
46 26
Measurements from IF input to audio output (pin 9) S/N (W) weighted signal-to-noise ratio referred to 54% FM modulation 6 kHz sinusoidal waveform black level white picture
560 between pins 13 and 11 CCIR468-4; with offset alignment on pin 4 black-to-white sync only 39 39 39 46 48 46 - - - dB dB dB
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
Notes to the characteristics 1. Typical values of video and sound parameters are decreased at VP = 4.5 V. 2. The input voltage for negative modulation has to be V8 > 1.5 V, or pin 8 open-circuit.
TDA9802
3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2 calculated with grey level and FPLL input signal level). Resonance circuit of VCO: Qo > 50; Cext = 8.2 pF; Cint 8.5 pF (loop voltage about 2.7 V). 4. The oscillator drift is related to the picture carrier frequency (at external temperature-compensated LC-circuit). 5. Vi IF = 10 mV (RMS value); f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture video modulation. 6. Vi IF for 0.9 V CVBS (peak-to-peak value) at composite video output pin 13; PLL is still locked. 7. Transformer at IF input (Fig.3). The C/N ratio at IF input for `lock-in' is defined as the vision IF input signal (sync level, RMS value) in relation to a superimposed, 5 MHz band-limited white noise signal (RMS value); video modulation: white picture. 8. Offset current measured between pin 6 and half of supply voltage (V = 2.5 V) under the following conditions: no input signal at IF input (pins 1 and 2) and IF-amplifier gain at minimum (V19 = VP), pin 4 (phase adjust) open-circuit. 9. The intercarrier output signal is superimposed to the video signal at pin 13 and can be calculated by the following formula: V iSC V 13 interc. ( p - p ) 20 log ----------------------------------------- = ----------- dB + 6.9 dB 2 dB V 1V ( p - p )
iPC
with V iSC ----------- dB = sound to picture carrier ratio at IF input (pins 1 and 2) in dB V iPC and 2 dB = tolerance of intercarrier output amplitude Vo FM. 10. Measurements taken with SAW filter G1956; modulation: VSB, fvideo > 0.5 MHz, loop bandwidth BL = 60 kHz. 11. The 7 dB buffer gain accounts for 1 dB loss in the sound trap. Buffer output signal is typical 2 V (p-p). If no sound trap is applied a 330 resistor must be connected from output to input (from pin 13 to pin 14). 12. The leakage current of the AGC capacitor has to be < 1 A in B/G mode (< 30 nA in L mode) to avoid larger tilt. 13. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value, pin 7). B = 5 MHz weighted in accordance with CCIR-567 at a source impedance of 50 . 14. 1.1 = 20 log (Vo at 4.4 MHz / Vo at 1.1 MHz) + 3.6 dB; 1.1 value at 1.1 MHz related to black/white signal 3.3 = 20 log (Vo at 4.4 MHz / Vo at 3.3 MHz); 3.3 value at 3.3 MHz related to colour carrier. 15. To match the AFC output signal to different tuning systems a current source output is provided (Fig.8). 16. Depending on the radio C/Co of the LC resonance circuit of VCO (Qo > 50; Co = Cint+Cext; Cext = 8.2 pF; Cint 8.5 pF). 17. No mute state is also valid for pin not connected. For switching on the L-standard no external load is allowed at pin 5 except capacitor CBL. 18. A 5.5 MHz signal for second IF with 10 mV (RMS value) input level, fmod = 1 kHz and frequency deviation with 54% FM modulation of audio reference is fed directly to pin 11. Audio measurements are taken at 50 s de-emphasis. 19. To allow higher frequency deviation, the resistor Rx on pin 10 (see Fig.12) has to be increased to a value which does not exceed the AF output signal of nominally 0.35 V for THD = 0.1% (Rx = 4.7 k provides -6 dB amplification). 20. The leakage current of the 2.2 F capacitor is < 100 nA.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
Fig.3 Test circuit.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
handbook, full pagewidth
70
MED332
GIF (dB)
60 I12 (mA) 0 40 (1) (2) (3) 30 (4) 0.6 0.2
50
20
1.0
10
1.4
0 -10
1.8 2.0 0 1 2 3 4 V19 (V) 5
Fig.4 IF AGC (dashed) and tuner AGC as a function of take over point adjustment.
handbook, halfpage
80
MED333
handbook, halfpage
-3.2 dB -13.2 dB -24 dB -10 dB
S/N (dB) 60
-13.2 dB -24 dB
40 SC CC BLUE 20 PC SC CC YELLOW
MED334
PC
SC = sound carrier level 0 -60 0.06 -40 0.6 -20 6 10 0 20
; with respect to TOP sync level.
CC = chrominance carrier level ; with respect to TOP sync level. PC = picture carrier level ; with respect to TOP sync level.
Vi IF(rms)(dB) 60 600 Vi IF(rms)(mV) Sound shelf attenuation: 17 dB.
Fig.5
Typical signal-to-noise ratio as a function of IF input signal.
Fig.6
Input conditions for intermodulation measurements.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
Fig.7 Video signal levels on output pin 13.
Fig.8 Measurement conditions and typical AFC characteristic.
Fig.9 Ripple rejection condition.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
handbook, full pagewidth
0
MED338
AM (dB) -20
-40
-60
-80
-100 10-1
1
10
102
Vi IC (mV)
103
Fig.10 Typical AM suppression of FM sound demodulator.
MED339
handbook, full pagewidth
370 Vo AF (mV RMS) 360 (1)
60 S/N (W) (dB) 50
(2) 350 40
340
30
330 10-1
20
1
10
102
Vi FM (mV)
103
Fig.11 Typical AF output signal and signal-to-noise ratio.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
(1) depends on tuner
Fig.12 Application circuit.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
(1) depends on TOP
Fig.13 Front end level diagram.
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
TDA9802
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Fig.14 Internal circuits.
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil)
TDA9802
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SO20: plastic small outline package; 20 leads; body width 7.5 mm
TDA9802
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.050 0.055 0.394 0.016
0.035 0.004 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA9802
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
November 1992
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Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and FM-PLL detector
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9802
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
November 1992
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